MAX-UP members frequently publish research work with Maxeler technology. On this page we highlight a few of these publications. If you would like your MAX-UP publication considered for inclusion here, please contact Cliff Winckless.
2023
High-Level Synthesis versus Hardware Construction
Alexander Kamkin†, Mikhail Chupilko†, Mikhail Lebedev†, Sergey Smolov†, Georgi Gaydadjiev§
†ISP RAS Plekhanov RUE, Russia §University of Groningen, Netherlands
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023
2021
Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons
Masashi Ogaki, Yukinori Sato
Toyohashi University of Technology, Toyohashi, Japan
International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 109-116, 2021
Reconfigurable Acceleration of Short Read Mapping with Biological Consideration
Ho-Cheung Ng†, Izaak Coleman§, Shuanglong Liu* and Wayne Luk†
†Imperial College London, UK §Columbia University, USA *Hunan Normal University, China
International Symposium on Field-Programmable Gate Arrays (FPGA), 2021
2020
Acceleration of Short Read Alignment with Runtime Reconfiguration
Ho-Cheung Ng et.al.
Imperial College London, London, UK
Field-Programmable Technology (FPT) 2020
High performance reconfigurable computing for numerical simulation and deep learning
L. Gan†, M. Yuan§, J. Yang*, et al.
†Tsinghua University, Beijing, China §Jiangnan University, Jiangsu, China *Imperial College London, London, UK
CCF Transactions on High Performance Computing 2:196–208 (2020)
A CGRA Definition Framework for Dataflow Applications
G. Charitopoulos† and D.N. Pnevmatikatos§
†Technical University of Crete, Greece §National Technical University of Athens, Greece
Applied Reconfigurable Computing (ARC), 2020
Enabling Dynamic System Integration on Maxeler HLS Platforms
C. Kritikakis and D. Koch
The University of Manchester, Manchster, UK
Journal of Signal Processing Systems 92:887–905 (2020)
2019
Time-SWAD: A Dataflow Engine for Time-based Single Window Stream Aggregation
P. Geethakumari, V. Gulisano, P. Trancoso, and I. Sourdis
Chalmers University of Technology, Sweden
Field Programmable Technology (FPT), 2019
Porting ESCAPE Cloud Microphysics Dwarf to an FPGA
J. Targett†, M. Lange§, and O. Marsden§
†Imperial College London, UK §ECMWF, UK
The Platform for Advanced Scientific Computing (PASC) Conference, 2019
Field-Programmable Gate Arrays and Quantum Monte Carlo: Power Efficient Co-processing for Scalable High-Performance Computing
Salvatore Cardamone, Jonathan R. Kimmitt, Hugh G. A. Burton, and Alex J. W. Thom
University of Cambridge, Cambridge, UK
Int J Quantum Chem. 2019. 119:e25853.
Exploring the DataFlow Supercomputing Paradigm
Veljko Milutinovic† and Milos Kotlar§
†Indiana University, USA §University of Belgrade, Serbia
Springer ISBN 978-3-030-13803-5, 2019
Scalable Filtering Modules for Database Acceleration on FPGAs
Kristiyan Manev, Anuj Vaishnav, Charalampos Kritikakis, and Dirk Koch
University of Manchester, UK
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), 2019
Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach
D. Masouros†, K. Koliogeorgi†, G. Zervakis†, A. Kosvyra§, A. Chytas§, S. Xydis†, I. Chouvarda§, D. Soudris†
†National Technical University of Athens, Greece §Aristotle University of Thessaloniki, Greece
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp. 622-625.
End-to-end Dynamic Stream Processing on Maxeler HLS Platforms
Charalampos Kritikakis and Dirk Koch
University of Manchester, UK
International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019
Designing and building application-centric parallel memories
Giulio Stramondo, Catalin Bogdan Ciobanu, Cees de Laat, and Ana Lucia Varbanescu
University of Amsterdam, The Netherlands
Concurrency and Computation: Practice and Experience, 2019;e5485.
Customisable Control Policy Learning for Robotics
Ce Guo†, Wayne Luk†, Stanley Qing Shui Loh†, Alexander Warren§, Joshua Levine§
†Imperial College London, UK §Intel Corporation, UK
International Conference on Application-specific Systems, Architectures and Processors (ASAP), Pages: 91-98, 2019
2018
Fast Sampling from Wiener Posteriors for Image Data with Dataflow Engines
Niall Jeffrey, Alan F. Heavens, Philip D. Fortio
Imperial College London, London, UK
Astronomy and Computing, Volume 25, Pages 230-237, ISSN 2213-1337, 2018
The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case
Harry Sidiropoulos†, George Chatzikonstantis†, Dimitrios Soudris†, Christos Strydis§
†ICCS, Greece §Erasmus University Medical Center Rotterdam, The Netherlands
Design and Architectures for Signal and Image Processing (DASIP), Porto, 2018, pp. 70-75.
Kalman Filter track reconstruction on FPGAs for acceleration of the High Level Trigger of the CMS experiment at the HL-LHC
Sioni Summers and Andrew Rose
Imperial College London, UK
23rd International Conference on Computing in High Energy and Nuclear Physics (CHEP 2018)
Lattice-based Scheduling for Multi-FPGA Systems
Teng Yu*, Bo Feng‡, Mark Stillwell†, Liucheng Guo†, Yuchun Ma‡, John Thomson*
*University of St Andrews, UK †Imperial College London, UK ‡Tsinghua University, China
International Conference on Field-Programmable Technology (FPT), 2018
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA
Ruizhe Zhao∗, Ho-Cheung Ng∗, Wayne Luk∗ and Xinyu Niu†
∗Imperial College London, UK †Corerain Technologies Ltd, Shenzhen, China
Field Programmable Logic and Applications (FPL) 2018
CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems
Andreea-Ingrid Cross∗, Liucheng Guo∗, Wayne Luk∗, and Mark Salmon†
∗Imperial College London, UK †Cambridge University, UK
Field Programmable Logic and Applications (FPL) 2018
DARSA: A dataflow analysis tool for reconfigurable platforms
George Charitopoulos and Dionisios N. Pnevmatikatos
Technical University of Crete, Greece
SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018
A performance evaluation of multi-FPGA architectures for computations of information transfer
Konstantinos Iordanou†, Sofia Maria Nikolakaki§, Pavlos Malakonakis†, Apostolos Dollas†
†Technical University of Crete, Greece §Boston University, USA
SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018
EXTRA: An Open Platform for Reconfigurable Architectures
Catalin Bogdan Ciobanu et.al.
SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018
The VINEYARD integrated framework for hardware accelerators in the cloud
C. Kachris†, D. Soudris†, S. Mavridis§, M. Pavlidakis§, C. Symeonidou§, C. Kozanitis§, A. Bilas§, D. Fenacci*, S. V. Bogaraju*, H. Vandierendonck*, D. S. Nikolopoulos*
†ICCS, Greece §FORTH, Greece *Queen’s University Belfast, UK
SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018
MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs
Catalin Bogdan Ciobanu, Giulio Stramondo, Cees de Laat, and Ana Lucia Varbanescu
University of Amsterdam, The Netherlands
IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) 2018: 107-114.
Towards Application-Centric Parallel Memories
Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, and Cees de Laat
University of Amsterdam, The Netherlands
Euro-Par 2018: Parallel Processing Workshops, LNCS, vol 11339. Springer, 2018
OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels
Francesco Peverelli, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio
Politecnico di Milano, Milan, Italy
IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) 2018: 91-98.
Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform
Chaim Baskin, Evgenii Zheltonozhskii, Alex M. Bronstein, Avi Mendelson, Natan Liss
Technion – Israel Institute of Technology, Haifa, Israel
IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) 2018: 162-169.
Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control
Shengjia Shao∗, Jason Tsai∗, Michal Mysior∗, Wayne Luk∗, Thomas Chau†, Alexander Warren† and Ben Jeppesen†
∗Imperial College London, UK †Intel, UK
International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations
Francis P. Russell, James Stanley Targett, and Wayne Luk
Imperial College London, UK
International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes
Achim Lösch, Marco Platzner
Paderborn University, Paderborn, Germany
International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
HLS Enabled Partially Reconfigurable Module Implementation
N.B. Grigore, C. Kritikakis, D. Koch
The University of Manchester, Manchester, UK
Architecture of Computing Systems (ARCS) LNCS, vol 10793. Springer, 2018
Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes
A. Lösch, A. Wiens, M. Platzner
Paderborn University, Paderborn, Germany
Architecture of Computing Systems (ARCS) LNCS, vol 10793. Springer, 2018
CJS: Custom Jacobi Solver
Andreea-Ingrid Cross∗, Liucheng Guo∗, Wayne Luk∗, and Mark Salmon†
∗Imperial College London, UK †Cambridge University, UK
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) 2018
Data-flow Conjugate Gradient Solver for Lattice QCD Calculations on FPGA Accelerator
Thomas Janson and Udo Kebschull
Goethe University Frankfurt, Germany
DPG Conference, HK 42.6, Bochum, Germany, February 2018
2017
BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations
G. Smaragdos†, G. Chatzikonstantis§, R. Kukreja$ , H. Sidiropoulos§, D. Rodopoulos**, I Sourdis*, Z. Al-Ars$, C. Kachris§, D. Soudris§, C. I De Zeeuw† and C Strydis†
† Neuroscience department, Erasmus MC, Rotterdam, Netherlands * Computer Science and Eng. department, Chalmers University of Technology, Gothenburg, Sweden § MicroLab, National Technical University of Athens, Athens, Greece $ Computer Eng. Lab, Delft University of Technology, Delft, Netherlands ** imec, Leuven, Belgium
Journal of Neural Engineering, vol. 14, No 6, IOP Publishing (2017).
FP-BNN: Binarized neural network on FPGA
Shuang Liang†, Shouyi Yin†, Leibo Liu†, Wayne Luk§, Shaojun Wei†
†Institute of Microelectronics, Tsinghua University, China, §Department of Computing, Imperial College London, UK
Neurocomputing, Volume 275, Pages 1072-1086. 2017.
A Fully-Pipelined Hardware Design for Gaussian Mixture Models
Conghui He, Haohuan Fu, Ce Guo, Wayne Luk and Guangwen Yang
IEEE Transactions on Computers, 66(11): 1837-1850 (2017)
Single window stream aggregation using reconfigurable hardware
P. Geethakumari, V. Gulisano, B. Svensson, P. Trancoso, and I. Sourdis
Chalmers University of Technology, Sweden
Field Programmable Technology (FPT), 2017
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project
Marco Rabozzi†, Rolando Brondolin†, Giuseppe Natale†, Emanuele Del Sozzo†, Michael Hübner§, Andreas Brokalakis+, Catalin B. Ciobanu*, Dirk Stroobandt**, Marco D. Santambrogio†
†Politecnico di Milano, Italy, §Ruhr-Universität Bochum, Germany, *Universiteit van Amsterdam, Netherlands +Synelixis, Greece **Ghent University, Belgium
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017: 368-373
Dataflow Acceleration of scikit-learn Gaussian Process Regression
Michail Doukas, Sotirios Xydis, Dimitrios Soudris
National Tech. University of Athens, Athens, Greece
Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM) 2017
Highly Parallel Lattice QCD Wilson Dirac Operator with FPGAs
Thomas Janson and Udo Kebschull
Goethe University Frankfurt, Germany
Advances in Parallel Computing (ParCo2017), Vol. 32,Pages 664-672, 2017
Efficient Branch and Bound on FPGAs using Work Stealing and Instance-Specific Designs
H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl
University of Paderborn
ACM Trans. on Reconfigurable Technology and Systems (TRETS). 2017.